1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within integrated circuits. More particularly, the present invention relates to methods for controlling and enhancing critical dimension uniformity of patterned photoresist layers employed in defining patterned layers within integrated circuits.
2. Background of the Invention
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
In the process of forming electrical circuit elements, patterned conductor layers and patterned dielectric layers within integrated circuits it is common in the art of integrated circuit fabrication to define the dimensions, and in particular the critical dimensions, of those electrical circuit elements, patterned conductor layers and patterned dielectric layers through etch methods which employ patterned photoresist layers as photoresist etch mask layers. While the use of patterned photoresist layers for defining within integrated circuits electrical circuit elements, patterned conductor layers and patterned dielectric layers has become quite common in the art, the methods through which are formed those patterned photoresist layers nonetheless still often provide patterned photoresist layers with significant critical dimension non-uniformity. The critical dimension non-uniformity often becomes significant as the magnitude of the critical dimension of patterned photoresist layers within integrated circuits becomes smaller, since within many photolithographic methods the critical dimension uniformity may remain constant while the critical dimension magnitude decreases. It is thus significant in the art of integrated circuit fabrication to devise methods through which the critical dimension uniformity within patterned photoresist layers may be controlled and enhanced while the critical dimension magnitude of those patterned photoresist layers is decreased. It is towards that goal that the present invention is generally directed.
Methods for monitoring and/or controlling the critical dimension uniformity of patterned photoresist layers employed as etch mask layers in defining patterned layers within integrated circuits are known in the art of integrated circuit fabrication. For example, Yoo in U.S. Pat. No. 5,324,689 discloses a method for controlling critical dimension of a patterned photoresist layer employed as an etch mask in forming a patterned polysilicon layer within an integrated circuit. The method employs a planarizing spin-on-glass layer formed interposed between a blanket photoresist layer and the polysilicon layer desired to be patterned. In addition, Corliss, in U.S. Pat. No. 5,427,878 discloses an optical endpoint detection method employing multiple sensors for controlling the endpoint and monitoring the critical dimension uniformity when forming a patterned layer, such as a patterned photoresist layer, upon a semiconductor substrate. From one of the multiple sensors there is controlled the endpoint when forming the patterned layer, while from the group of multiple sensors there is determined the critical dimension uniformity of the patterned layer.
While Corliss' method bears particular relevance to the problem towards which the present invention is directed, Corliss' method by employing endpoint detection seeks inherently to compensate for all parametric variations encountered when forming a patterned layer, such as a patterned photoresist layer, by controlling either a blanket photoresist layer development time or a blanket layer etch time. Thus, while Corliss' method provides improved integrated circuit layer process control and monitoring, Corliss' method provides neither optimal process flexibility nor optimal critical dimension uniformity in forming within integrated circuits patterned layers, such as patterned photoresist layers.
Thus, desirable in the art are additional methods through which critical dimension uniformity may be controlled and enhanced, with enhanced process flexibility, within patterned photoresist layers which are employed in defining patterned layers within integrated circuits. It is towards the foregoing goal that the present invention is specifically directed.